arm64-asm.h 3.8 KB

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  1. /*
  2. * @APPLE_LICENSE_HEADER_START@
  3. *
  4. * Copyright (c) 2018 Apple Inc. All Rights Reserved.
  5. *
  6. * This file contains Original Code and/or Modifications of Original Code
  7. * as defined in and that are subject to the Apple Public Source License
  8. * Version 2.0 (the 'License'). You may not use this file except in
  9. * compliance with the License. Please obtain a copy of the License at
  10. * http://www.opensource.apple.com/apsl/ and read it before using this
  11. * file.
  12. *
  13. * The Original Code and all software distributed under the License are
  14. * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  15. * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  16. * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  18. * Please see the License for the specific language governing rights and
  19. * limitations under the License.
  20. *
  21. * @APPLE_LICENSE_HEADER_END@
  22. */
  23. /********************************************************************
  24. *
  25. * arm64-asm.h - asm tools for arm64/arm64_32 and ROP/JOP
  26. *
  27. ********************************************************************/
  28. #if __arm64__
  29. #if __LP64__
  30. // true arm64
  31. #define SUPPORT_TAGGED_POINTERS 1
  32. #define PTR .quad
  33. #define PTRSIZE 8
  34. #define PTRSHIFT 3 // 1<<PTRSHIFT == PTRSIZE
  35. // "p" registers are pointer-sized
  36. #define UXTP UXTX
  37. #define p0 x0
  38. #define p1 x1
  39. #define p2 x2
  40. #define p3 x3
  41. #define p4 x4
  42. #define p5 x5
  43. #define p6 x6
  44. #define p7 x7
  45. #define p8 x8
  46. #define p9 x9
  47. #define p10 x10
  48. #define p11 x11
  49. #define p12 x12
  50. #define p13 x13
  51. #define p14 x14
  52. #define p15 x15
  53. #define p16 x16
  54. #define p17 x17
  55. // true arm64
  56. #else
  57. // arm64_32
  58. #define SUPPORT_TAGGED_POINTERS 0
  59. #define PTR .long
  60. #define PTRSIZE 4
  61. #define PTRSHIFT 2 // 1<<PTRSHIFT == PTRSIZE
  62. // "p" registers are pointer-sized
  63. #define UXTP UXTW
  64. #define p0 w0
  65. #define p1 w1
  66. #define p2 w2
  67. #define p3 w3
  68. #define p4 w4
  69. #define p5 w5
  70. #define p6 w6
  71. #define p7 w7
  72. #define p8 w8
  73. #define p9 w9
  74. #define p10 w10
  75. #define p11 w11
  76. #define p12 w12
  77. #define p13 w13
  78. #define p14 w14
  79. #define p15 w15
  80. #define p16 w16
  81. #define p17 w17
  82. // arm64_32
  83. #endif
  84. #if __has_feature(ptrauth_returns)
  85. // ROP
  86. # define SignLR pacibsp
  87. # define AuthenticateLR autibsp
  88. #else
  89. // not ROP
  90. # define SignLR
  91. # define AuthenticateLR
  92. #endif
  93. #if __has_feature(ptrauth_calls)
  94. // JOP
  95. .macro TailCallFunctionPointer
  96. // $0 = function pointer value
  97. braaz $0
  98. .endmacro
  99. .macro TailCallCachedImp
  100. // $0 = cached imp, $1 = address of cached imp, $2 = SEL, $3 = isa
  101. eor $1, $1, $2 // mix SEL into ptrauth modifier
  102. eor $1, $1, $3 // mix isa into ptrauth modifier
  103. brab $0, $1
  104. .endmacro
  105. .macro TailCallMethodListImp
  106. // $0 = method list imp, $1 = address of method list imp
  107. braa $0, $1
  108. .endmacro
  109. .macro TailCallBlockInvoke
  110. // $0 = invoke function, $1 = address of invoke function
  111. braa $0, $1
  112. .endmacro
  113. .macro AuthAndResignAsIMP
  114. // $0 = cached imp, $1 = address of cached imp, $2 = SEL, $3 = isa
  115. // note: assumes the imp is not nil
  116. eor $1, $1, $2 // mix SEL into ptrauth modifier
  117. eor $1, $1, $3 // mix isa into ptrauth modifier
  118. autib $0, $1 // authenticate cached imp
  119. ldr xzr, [$0] // crash if authentication failed
  120. paciza $0 // resign cached imp as IMP
  121. .endmacro
  122. // JOP
  123. #else
  124. // not JOP
  125. .macro TailCallFunctionPointer
  126. // $0 = function pointer value
  127. br $0
  128. .endmacro
  129. .macro TailCallCachedImp
  130. // $0 = cached imp, $1 = address of cached imp, $2 = SEL, $3 = isa
  131. eor $0, $0, $3
  132. br $0
  133. .endmacro
  134. .macro TailCallMethodListImp
  135. // $0 = method list imp, $1 = address of method list imp
  136. br $0
  137. .endmacro
  138. .macro TailCallBlockInvoke
  139. // $0 = invoke function, $1 = address of invoke function
  140. br $0
  141. .endmacro
  142. .macro AuthAndResignAsIMP
  143. // $0 = cached imp, $1 = address of cached imp, $2 = SEL
  144. eor $0, $0, $3
  145. .endmacro
  146. // not JOP
  147. #endif
  148. #define TailCallBlockInvoke TailCallMethodListImp
  149. // __arm64__
  150. #endif